1. Field of the Invention
The present invention relates to the data storage field; more specifically, the present invention relates to a non-volatile semiconductor memory device.
2. Description of the Related Art
Non-volatile memory devices are commonly used to store information which must be preserved also in absence of an electric power source that supply the memory device. A particular class of non-volatile memory devices is electrically programmable, like flash E2PROM. Typically, the memory device includes a matrix of memory cells, for example arranged in rows and columns. Each memory cell consists of a floating gate MOS transistor programmed by injecting an electric charge into its floating gate; on the contrary, the transistor is erased by removing the electric charge from its floating gate. The electric charge in the floating gate modifies the threshold voltage of the transistor, in such a way as to define different logic values.
The memory device further includes a bit line for each column of the matrix, and a word line for each matrix row. A typical matrix architecture is the so-called NOR architecture, according to which the generic cell is positioned at the crossing of the bit line and the word line corresponding to the column and row that the cell belongs to, and all the cells of a same column are connected, in parallel to each other and by their drain terminal, to a same bit line.
A read operation of the memory cells provides for biasing them in prescribed read operating conditions, and detecting the current that the memory cells sink. Particularly, during a reading phase of flash memory cells, it is necessary to bias the addressed bit lines, to which the cells belong, at a reading voltage Vpr, typically 1V.
The bit lines are conductive lines photolithographically obtained from, e.g., a metal layer. The unavoidable capacitive coupling between selected bit lines (access bit lines) and bit lines adjacent thereto (side bit lines) causes the generation of a current noise signal on the selected bit lines. This capacitive coupling is due to the fact that, owing to the ultra-large scale of integration, the distance (pitch) between adjacent bit lines in modern memory devices becomes smaller and smaller. Said current noise signal adds up to the reading current of the selected cell during its read operation. During the selected bit line charging (from a starting voltage substantially equal to the ground voltage to the reading voltage Vpr), the adjacent bit lines are capacitively brought towards a voltage value equal to a fraction of the voltage Vpr. Then, the side bit lines discharge in a way that depends on the programming state of the memory cells adjacent to the accessed memory cell (that is, the memory cells belonging to the same word line as the selected cell, and to the bit lines adjacent to the accessed bit line). In fact, if both of the immediately adjacent cells are programmed (high threshold voltage), and thus do not conduct current, the side bit lines do not discharge and remain at the voltage value reached during the charging phase. On the contrary, if one of the adjacent cells is not programmed (low threshold voltage), thereby conducting current, the bit line corresponding to the unprogrammed cell discharges toward ground. In short, both, only one, or none of the side bit lines may discharge toward ground, depending on the state of the adjacent memory cells. Consequently, during the reading phase of a memory cell, a noise current In is superimposed on the cell current Ir, and this noise current In depends on the adjacent memory cells state, so its value can not be forecasted in the design phase. In the case of so-called “multilevel” memory devices, whose memory cells can be programmed in more than two states, the current sunk by each memory cell has more than two possible values, so the noise current is even more variable.
The total current (I=Ir+In) the sense amplifier receives at its input might determine the detection of a value different from the one actually stored in the accessed cell.
This problem of bit line capacitive coupling, also referred to as the “fringing” effect problem, results particularly critical when the current difference between different logic values that the cell reading current Ir may take, depending on the logic value stored therein, is small, as for example in the case of multilevel memory devices.
In view of the state of the art outlined in the foregoing, the Applicant has faced the problem of how to avoid or at least reduce the problem of reading errors caused by fringing effects on the bit lines.